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<div class="title">XFpgatag Struct Reference<div class="ingroups"><a class="el" href="group__xilfpga__zynq__versal.html">XilFPGA APIs for Versal Adative SoC and Zynq UltraScale+ MPSoC</a></div></div>  </div>
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<p>Structure to the XFpga instance.
 <a href="struct_x_fpgatag.html#details">More...</a></p>
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Data Fields</h2></td></tr>
<tr class="memitem:a17d90caf2f96a1c0ce3a309015fd32ae"><td class="memItemLeft" align="right" valign="top">u32(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html#a17d90caf2f96a1c0ce3a309015fd32ae">XFpga_ValidateBitstream</a> )(struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td></tr>
<tr class="memdesc:a17d90caf2f96a1c0ce3a309015fd32ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Validate the bitstream header before programming the PL.  <a href="#a17d90caf2f96a1c0ce3a309015fd32ae">More...</a><br/></td></tr>
<tr class="separator:a17d90caf2f96a1c0ce3a309015fd32ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a542049e29b0804aabea8bcc577d71b47"><td class="memItemLeft" align="right" valign="top">u32(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html#a542049e29b0804aabea8bcc577d71b47">XFpga_PreConfig</a> )(struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td></tr>
<tr class="memdesc:a542049e29b0804aabea8bcc577d71b47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prepare the FPGA to receive confuration data.  <a href="#a542049e29b0804aabea8bcc577d71b47">More...</a><br/></td></tr>
<tr class="separator:a542049e29b0804aabea8bcc577d71b47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a31407cee8cfa8d58cea94bda3147e757"><td class="memItemLeft" align="right" valign="top">u32(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html#a31407cee8cfa8d58cea94bda3147e757">XFpga_WriteToPl</a> )(struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td></tr>
<tr class="memdesc:a31407cee8cfa8d58cea94bda3147e757"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write count bytes of configuration data to the FPGA.  <a href="#a31407cee8cfa8d58cea94bda3147e757">More...</a><br/></td></tr>
<tr class="separator:a31407cee8cfa8d58cea94bda3147e757"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3e5baa8aaa7b73f6cd31737b2465515c"><td class="memItemLeft" align="right" valign="top">u32(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html#a3e5baa8aaa7b73f6cd31737b2465515c">XFpga_PostConfig</a> )(struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td></tr>
<tr class="memdesc:a3e5baa8aaa7b73f6cd31737b2465515c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set FPGA to operating state after writing is done.  <a href="#a3e5baa8aaa7b73f6cd31737b2465515c">More...</a><br/></td></tr>
<tr class="separator:a3e5baa8aaa7b73f6cd31737b2465515c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a088ada7ce0d61319dafb5bfd85290cb1"><td class="memItemLeft" align="right" valign="top">u32(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html#a088ada7ce0d61319dafb5bfd85290cb1">XFpga_GetFeatureList</a> )(struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td></tr>
<tr class="memdesc:a088ada7ce0d61319dafb5bfd85290cb1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets the feature list that xilfpga library supports.  <a href="#a088ada7ce0d61319dafb5bfd85290cb1">More...</a><br/></td></tr>
<tr class="separator:a088ada7ce0d61319dafb5bfd85290cb1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6af355b88beaac6b872a53c13285514b"><td class="memItemLeft" align="right" valign="top">u32(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html#a6af355b88beaac6b872a53c13285514b">XFpga_GetInterfaceStatus</a> )(void)</td></tr>
<tr class="memdesc:a6af355b88beaac6b872a53c13285514b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Provides the STATUS of PL programming interface.  <a href="#a6af355b88beaac6b872a53c13285514b">More...</a><br/></td></tr>
<tr class="separator:a6af355b88beaac6b872a53c13285514b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a112c731b7c08c57308e95856658fae97"><td class="memItemLeft" align="right" valign="top">u32(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html#a112c731b7c08c57308e95856658fae97">XFpga_GetConfigReg</a> )(const struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td></tr>
<tr class="memdesc:a112c731b7c08c57308e95856658fae97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns the value of the specified configuration register.  <a href="#a112c731b7c08c57308e95856658fae97">More...</a><br/></td></tr>
<tr class="separator:a112c731b7c08c57308e95856658fae97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af817a3d9e50e29ae60448178d216df29"><td class="memItemLeft" align="right" valign="top">u32(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html#af817a3d9e50e29ae60448178d216df29">XFpga_GetConfigData</a> )(const struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td></tr>
<tr class="memdesc:af817a3d9e50e29ae60448178d216df29"><td class="mdescLeft">&#160;</td><td class="mdescRight">Provides the FPGA readback data.  <a href="#af817a3d9e50e29ae60448178d216df29">More...</a><br/></td></tr>
<tr class="separator:af817a3d9e50e29ae60448178d216df29"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a95e48f781a288df71e5ee599d78532b6"><td class="memItemLeft" align="right" valign="top">XFpga_Info&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html#a95e48f781a288df71e5ee599d78532b6">PLInfo</a></td></tr>
<tr class="memdesc:a95e48f781a288df71e5ee599d78532b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure which is used to store the secure image data.  <a href="#a95e48f781a288df71e5ee599d78532b6">More...</a><br/></td></tr>
<tr class="separator:a95e48f781a288df71e5ee599d78532b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acd5464c8e6c66bf80aa0139efe016bb7"><td class="memItemLeft" align="right" valign="top">XFpga_Read&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html#acd5464c8e6c66bf80aa0139efe016bb7">ReadInfo</a></td></tr>
<tr class="memdesc:acd5464c8e6c66bf80aa0139efe016bb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure which is used to store the PL Image readback details.  <a href="#acd5464c8e6c66bf80aa0139efe016bb7">More...</a><br/></td></tr>
<tr class="separator:acd5464c8e6c66bf80aa0139efe016bb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a43bcd659f5043721bf8f99df22330a19"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_fpga___write.html">XFpga_Write</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_fpgatag.html#a43bcd659f5043721bf8f99df22330a19">WriteInfo</a></td></tr>
<tr class="memdesc:a43bcd659f5043721bf8f99df22330a19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure which is used to store the PL Write Image details.  <a href="#a43bcd659f5043721bf8f99df22330a19">More...</a><br/></td></tr>
<tr class="separator:a43bcd659f5043721bf8f99df22330a19"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Structure to the XFpga instance. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a95e48f781a288df71e5ee599d78532b6"></a>
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          <td class="memname">XFpga_Info XFpgatag::PLInfo</td>
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<p>Structure which is used to store the secure image data. </p>

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<p>Structure which is used to store the PL Image readback details. </p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq__versal.html#ga5e98e018395a91d666b1bf5322ead85a">XFpga_GetPlConfigData()</a>, and <a class="el" href="group__xilfpga__zynq__versal.html#ga16b3f58643bb4ca44b5f76cb15ca3c27">XFpga_GetPlConfigReg()</a>.</p>

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<a class="anchor" id="a43bcd659f5043721bf8f99df22330a19"></a>
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          <td class="memname"><a class="el" href="struct_x_fpga___write.html">XFpga_Write</a> XFpgatag::WriteInfo</td>
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<p>Structure which is used to store the PL Write Image details. </p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq__versal.html#ga44b0cd1361ba0ff98ceed775997bc23b">XFpga_BitStream_Load()</a>, <a class="el" href="group__xilfpga__zynq__versal.html#gab9954493b57ad172167f25a3aa1b0eb0">XFpga_ValidateImage()</a>, and <a class="el" href="group__xilfpga__zynq__versal.html#ga3801d1f23178289fb912ecc61cdc018d">XFpga_Write_Pl()</a>.</p>

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          <td class="memname">u32(* XFpgatag::XFpga_GetConfigData)(const struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td>
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<p>Provides the FPGA readback data. </p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq__versal.html#ga5e98e018395a91d666b1bf5322ead85a">XFpga_GetPlConfigData()</a>, and <a class="el" href="group__xilfpga__zynq__versal.html#gaef5fb78d2b7e74b3a4f3b18ebf0a3599">XFpga_Initialize()</a>.</p>

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          <td class="memname">u32(* XFpgatag::XFpga_GetConfigReg)(const struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td>
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<p>Returns the value of the specified configuration register. </p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq__versal.html#ga16b3f58643bb4ca44b5f76cb15ca3c27">XFpga_GetPlConfigReg()</a>, and <a class="el" href="group__xilfpga__zynq__versal.html#gaef5fb78d2b7e74b3a4f3b18ebf0a3599">XFpga_Initialize()</a>.</p>

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          <td class="memname">u32(* XFpgatag::XFpga_GetFeatureList)(struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td>
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<p>Gets the feature list that xilfpga library supports. </p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq.html#gaef5fb78d2b7e74b3a4f3b18ebf0a3599">XFpga_Initialize()</a>.</p>

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<p>Provides the STATUS of PL programming interface. </p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq__versal.html#gaef5fb78d2b7e74b3a4f3b18ebf0a3599">XFpga_Initialize()</a>, and <a class="el" href="group__xilfpga__zynq__versal.html#ga2f8e3aaa97c67aaaae6521f75f989e59">XFpga_InterfaceStatus()</a>.</p>

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          <td class="memname">u32(* XFpgatag::XFpga_PostConfig)(struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td>
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<p>Set FPGA to operating state after writing is done. </p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq.html#gaef5fb78d2b7e74b3a4f3b18ebf0a3599">XFpga_Initialize()</a>, and <a class="el" href="group__xilfpga__zynq__versal.html#gae97b4dd15b87b8a9931a242bb855e031">XFpga_PL_PostConfig()</a>.</p>

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          <td class="memname">u32(* XFpgatag::XFpga_PreConfig)(struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td>
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<p>Prepare the FPGA to receive confuration data. </p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq.html#gaef5fb78d2b7e74b3a4f3b18ebf0a3599">XFpga_Initialize()</a>, and <a class="el" href="group__xilfpga__zynq__versal.html#gade4f3d3efdce2034be71f597e84a667c">XFpga_PL_Preconfig()</a>.</p>

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          <td class="memname">u32(* XFpgatag::XFpga_ValidateBitstream)(struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td>
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<p>Validate the bitstream header before programming the PL. </p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq.html#gaef5fb78d2b7e74b3a4f3b18ebf0a3599">XFpga_Initialize()</a>, and <a class="el" href="group__xilfpga__zynq__versal.html#gab9954493b57ad172167f25a3aa1b0eb0">XFpga_ValidateImage()</a>.</p>

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          <td class="memname">u32(* XFpgatag::XFpga_WriteToPl)(struct <a class="el" href="struct_x_fpgatag.html">XFpgatag</a> *InstancePtr)</td>
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<p>Write count bytes of configuration data to the FPGA. </p>

<p>Referenced by <a class="el" href="group__xilfpga__zynq__versal.html#gaef5fb78d2b7e74b3a4f3b18ebf0a3599">XFpga_Initialize()</a>, and <a class="el" href="group__xilfpga__zynq__versal.html#ga3801d1f23178289fb912ecc61cdc018d">XFpga_Write_Pl()</a>.</p>

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